? semiconductor components industries, llc, 2003 october, 2003 ? rev. 2 1 publication order number: nb100elt23l/d nb100elt23l 3.3vdual differential lvpecl to lvttl translator the nb100elt23l is a dual differential lvpecl to lvttl translator. because lvpecl (positive ecl) levels are used, only +3.3 v and ground are required. the small outline 8-lead package and the dual gate design of the elt23l m akes it ideal for applications which require the translation of a clock and a data signal. the elt23l is available in only the ecl 100k standard. since there are no lvpecl outputs or an external v bb reference, the elt23l does not require both ecl standard versions. the lvpecl inputs are differential. therefore, the nb 100elt23l can accept any standard differential lvpecl input referenced from a v cc of +3.3 v. ? 2.1 ns typical propagation delay ? maximum operating frequency > 160 mhz ? 24 ma lvttl outputs ? operating range: v cc = 3.0 v to 3.6 v with gnd = 0 v ? open input default state ? q output will default low with inputs open or at gnd device package shipping 2 ordering information NB100ELT23LD so?8 98 units/rail NB100ELT23LDr2 so?8 2500 tape & reel NB100ELT23LDt tssop?8 100 units/rail NB100ELT23LDtr2 tssop?8 2500 tape & reel *for additional information, see application note and8002/d marking diagrams* a = assembly location l = wafer lot y = year w = work week alyw kt23l alyw k23l so?8 d suffix case 751 1 8 tssop?8 dt suffix case 948r 1 8 1 8 1 8 http://onsemi.com 2for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb100elt23l http://onsemi.com 2 1 2 3 45 6 7 8 q0 gnd v cc figure 1. 8?lead pinout (top view) and logic diagram d0 q1 d1 d1 d0 lvpecl lvttl pin description pin q0, q1 d0**, d1** d0 **, d1 ** differential lvpecl inputs function lvttl outputs v cc positive supply gnd ground ** pins will default to v cc /2 when left open. attributes characteristics value internal input pulldown resistor 50 k internal input pullup resistor 50 k esd protection human body model machine model charged device model > 1.2 kv > 150 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) level 1 flammability rating oxygen index: 28 to 34 ul 94 v?0 @ 1.25 in transistor count 91 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc power supply gnd = 0 v 3.8 v v in p ut voltage gnd 0 v v v 38 v v i input voltage gnd = 0 v v i v cc 3.8 v i out output current continuous surge 50 100 ma ma ta operating temperature range ?40 to +85 c t stg storage temperature range ?65 to +150 c ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm 8 soic 8 soic 190 130 c/w c/w jc thermal resistance (junction?to?case) std bd 8 soic 41 to 44 c/w ja thermal resistance (junction?to?ambient) 0 lfpm 500 lfpm 8 tssop 8 tssop 185 140 c/w c/w jc thermal resistance (junction?to?case) std bd 8 tssop 41 to 44 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur.
nb100elt23l http://onsemi.com 3 pecl dc characteristics v cc = 3.3 v, gnd = 0 v (note 3) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i cch power supply current (outputs set to high) 10 14 20 10 15 20 10 15 20 ma i ccl power supply current (outputs set to low) 15 19 25 15 19 25 15 20 25 ma v ih input high voltage 2075 2420 2075 2420 2075 2420 mv v il input low voltage 1355 1675 1355 1675 1355 1675 mv v ihcmr input high voltage common mode range (note 4) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 a i il input low current 0.5 0.5 0.5 a note: circuits are desi gned to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. all values vary 1:1 with v cc . 4. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. ttl dc characteristics v cc = 3.3 v, gnd = 0.0 v, t a = ?40 c to 85 c symbol characteristic condition min typ max unit v oh output high voltage i oh = ?3.0 ma 2.4 v v ol output low voltage i ol = 24 ma 0.5 v i os output short circuit current ?180 ?50 ma note: circuits are desi gned to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. ac characteristics v cc = 3.3 v 5%, gnd = 0.0 v (note 5) ?40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency 160 160 160 mhz t plh , t phl propagation delay to output differential (note 6) c l = 20 pf 1.5 2.1 2.75 1.5 2.1 2.75 1.5 2.1 2.75 ns t sk+ + t sk? ? t skpp output?to?output skew++ output?to?output skew? ? part?to?part skew (note 7) 60 25 500 60 25 500 60 25 500 ps t jitter random clock jitter (rms) 0.2 < 1 0.2 < 1 0.2 < 1 ps v pp input voltage swing (differential configuration) 150 800 1200 150 800 1200 150 800 1200 mv t r t f output rise/fall times c l = 20 pf (1.0 v ? 2.0 v) q 500 300 1300 1000 500 300 1300 1000 500 300 1300 1000 ps 5. measured using a 750 mv source, 50% duty cycle clock source. all loading with 500 to gnd, c l = 20 pf. 6. reference (v cc = 3.3 v 5%; gnd = 0 v) 7. skews are measured between outputs under identical conditions.
nb100elt23l http://onsemi.com 4 figure 2. ttl output loading used for device evaluation characteristic test c l *r l ac test load gnd *c l includes fixture capacitance application ttl receiver resource reference of application notes an1404 ? eclinps circuit performance at non?standard v ih levels an1405 ? ecl clock distribution techniques an1406 ? designing with pecl (ecl at +5.0 v) an1503 ? eclinps i/o spice modeling kit an1504 ? metastability and the eclinps family an1560 ? low voltage eclinps spice modeling kit an1568 ? interfacing between lvds and ecl an1596 ? eclinps lite translator elt family spice i/o model kit an1650 ? using wire?or ties in eclinps designs an1672 ? the ecl translator guide and8001 ? odd number counters design and8002 ? marking and date codes and8020 ? termination of ecl logic devices for an updated list of application notes, please see our website at http://onsemi.com.
nb100elt23l http://onsemi.com 5 package dimensions so?8 d suffix plastic soic package case 751?07 issue aa seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751-01 thru 751-06 are obsolete. new standaard is 751-07 a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m
nb100elt23l http://onsemi.com 6 package dimensions dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.80 1.10 0.031 0.043 d 0.05 0.15 0.002 0.006 f 0.40 0.70 0.016 0.028 g 0.65 bsc 0.026 bsc l 4.90 bsc 0.193 bsc m 0 6 0 6 seating plane pin 1 1 4 85 detail e b c d a g detail e f m l 2x l/2 ?u? s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 8x ref k ident k 0.25 0.40 0.010 0.016 tssop?8 dt suffix plastic tssop package case 948r?02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane -w-. on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 nb100elt23l/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
|
